library ieee;
use ieee.std_logic_1164.all;

entity accu_n is
	generic (
		N : integer := 16
	);
	port (
		clk_i 	 : in  std_logic;
		nreset_i : in  std_logic;
		x_i   	 : in  std_logic_vector(N-1 downto 0);
		y_o		 : out std_logic_vector(N-1 downto 0)
	);
end accu_n;

architecture behav of accu_n is
	component register_n
		generic (
			N : integer := 4
		);
		port (
			clk_i 	 : in  std_logic;
			nreset_i : in  std_logic;
			we_i	 : in  std_logic;
			d_i      : in  std_logic_vector(N-1 downto 0);
			q_o      : out std_logic_vector(N-1 downto 0)
		);
	end component;

	component adder_n
		generic (
			N : integer := 4
		);
		port (
			a_i    : in  std_logic_vector(N-1 downto 0);
			b_i    : in  std_logic_vector(N-1 downto 0);
			cin_i  : in  std_logic;
			y_o    : out std_logic_vector(N-1 downto 0);
			cout_o : out std_logic
		);
	end component;

	signal r_x : std_logic_vector(N-1 downto 0);
	signal s_x : std_logic_vector(N-1 downto 0);

begin

	adder_inst : adder_n generic map (
		N => N
	) port map (
		a_i   	=> x_i, 
		b_i    	=> r_x,
		cin_i   => '0',
		y_o     => s_x,
		cout_o  => open
	);
	
	reg_inst : register_n generic map (
		N => N
	) port map (
		clk_i 	 => clk_i, 
		nreset_i => nreset_i,
		we_i	 => '1',
		d_i      => s_x,
		q_o      => r_x
	);

	y_o <= s_x;

end behav;
